For each succeeding generation of integrated circuits, both transistor speed and density has increased. As the term is used herein, “integrated circuit” includes devices such as those formed on monolithic semiconducting substrates, such as those formed of group IV materials like silicon or germanium, or group III–V compounds like gallium arsenide, or mixtures of such materials. The term includes all types of devices formed, such as memory and logic, and all designs of such devices, such as MOS and bipolar. The term also comprehends applications such as flat panel displays, solar cells, and charge coupled devices.
To increase the transistor density of integrated circuits, the metal line width, via diameters, and space for electrically conductive interconnects has been reduced during the succeeding generations. This reduction in the size of electrically conductive line spacing tends to increase the capacitance effects that exist between the conductive elements, which in turn tends to increase the resistance-capacitance delay exhibited by the interconnections, and further results in a delay in the overall response of the integrated circuit. At the 130 nanometer gate technology node, the metal interconnect resistance-capacitance delay becomes an significant factor in the design speed of the integrated circuit.
To address this delay issue, the semiconductor fabrication industry has widely adapted the use of copper as an electrically conductive interconnect material, to generally replace aluminum. This use of copper is an effort to reduce the resistivity of interconnect structure. On the other hand, to reduce the capacitance between interconnects, the dielectric constant, or k value, of the electrically insulating materials disposed between the interconnects is desirably reduced. Thus, fluorine doped silicon dioxide, which has a k value of about 3.7, was introduced at the 180 nanometer technology node. However, the practice of adapting those electrically insulating materials that have a k value of between about 2.6 and 3.0 for the 130 nanometer technology node has introduced problematic process, reliability, and yield issues.
The integration of materials on the lower end of the k value range has proven to be even more challenging. One difficulty involved in the integration of these so-called low k materials is that to achieve a dielectric constant of less than about 2.9, the low k materials generally need to be porous. The porous low-k dielectric materials tend to be very fragile and lack mechanical strength, and thus present tremendous challenges for the back-end process technologies such as dielectric deposition, chemical mechanical polishing, and etching.
For example, FIG. 1 depicts cracking 3 of a low-k film 5 after an anneal process. FIG. 2 depicts a trench 7 formed in a low k material 9, after exposure to an oxygen plasma that has aggressively attacked the porous low k material. Thus, further reduction of dielectric k values and fabricating interconnect structures that are compatible with the new materials and processes tend to be some of the major challenges of back-end processing. Various solutions have been proposed for these problems. For example, the industry can continue to develop low k materials and deposition technologies, and implement barrier layers to protect the low k structures. Another option is to continue to develop new process technologies such as via etch, trench etch, dielectric chemical mechanical polishing, and interconnect deposition for each new generation of low k film. A further option is to continue to invest in new equipment that is designed to overcome these issues in some manner.
However, all of the options thus presented tend to have one or more severe disadvantage. For example, the inherent problems of fragility, lack of mechanical strength, and weak chemical properties for porous low k materials are hard to overcome from the process and integration perspective. The difficulties associated with processing and integration of the low k materials tend to increase dramatically with the decrease of the k value. These difficulties tend to limit the scalability of continuing to reduce the k value of the insulating materials. Additionally, there are reliability and yield issues associated with the processing and integration of low k materials. Such solutions tend to require a relatively large capital investment, and tend to delay the time to market of the integrated circuits so fabricated.
What is needed, therefore, is a system that at least reduces in part some of the problems described above.